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Integrated Circuit Systems, Inc.
ICS950403
Advance Information
AMD - K8TM System Clock Chip
Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset
Pin Configuration
*FS0/REF0 1 48 REF1/FS1*
Output Features: VDDREF 2 47 GND * 2 - Differential pair push-pull CPU clocks @ X1 3 46 VDDREF 3.3V X2 4 45 REF2/FS2* * 9 - PCICLK (Including 1 free running) @ 3.3V GND 5 44 Reset# * 3 - Selectable PCICLK/HTTCLK @ 3.3V ~*ModeA/HTTCLK0 6 43 VDDA ~*ModeB/PCICLK7/HTTCLK1 7 42 GND * 1 - HTTCLK @ 3.3V ~PCICLK8/HTTCLK2 8 41 CPUCLK8T0 * 1 - 48MHz @ 3.3V fixed. VDDPCI 9 40 CPUCLK8C0 * 1 - 24/48MHz @ 3.3V GND 10 39 GND * 3 - REF @ 3.3V, 14.318MHz. ~PCICLK9/HTTCLK3 11 38 VDDCPU Features: PCICLK10 12 37 CPUCLK8T1 * Programmable output frequency. PCICLK0 13 36 CPUCLK8C1 PCICLK1 14 35 VDDCPU * Programmable output divider ratios. GND 15 34 GND * Programmable output rise/fall time. VDDPCI 16 33 GND * Programmable output skew. ~PCICLK2 17 32 PD#* * Programmable spread percentage for EMI ~PCICLK3 18 31 48MHz/FS3** control. VDDPCI 19 30 GND * Watchdog timer technology and RESET# output GND 20 29 AVDD48 to reset system PCICLK4 21 28 24_48MHz/Sel24_48#*~ if system malfunctions. PCICLK5 22 27 GND ~PCICLK_F 23 26 SDATA * Programmable watch dog safe frequency. ~PCICLK6 24 25 SCLK 2 * Support I C Index read/write and block read/ 48-SSOP write operations. * Internal Pull-Up Resistor * Uses external 14.318MHz crystal. ** Internal Pull-Down Resistor * Supports Hyper Transport Technology (HTTCLK).
~ This Output has 2X Drive Strength
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum
Functionality
48MHz 24_48MHz
ICS950403
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
REF (2:0)
CPU DIVDER
CPUCLKC (1:0) CPUCLKT (1:0)
PD# SDATA SCLK FS (3:0) MODE (A,B) SEL24_48# Control Logic Config. Reg.
PCI DIVDER
Stop
PCICLK (6:0, 10) PCICLK_F
X2
PCICLK/HTTCLK (3:1)
HTTCLK0
CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 150.00 180.00 210.00 240.00 270.00 233.33 266.67 300.00
HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00
PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 30.00 30.00 35.00 30.00 33.75 33.33 33.33 37.50
0732--01/27/03 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS950403
Advance Information
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN TYPE I/O *FS0/REF0 VDDREF PWR X1 IN X2 OUT GND PWR ~*ModeA/HTTCLK0 I/O ~*ModeB/PCICLK7/HTTCLK I/O ~PCICLK8/HTTCLK2 OUT VDDPCI PWR GND PWR ~PCICLK9/HTTCLK3 OUT PCICLK10 OUT PCICLK0 OUT PCICLK1 OUT GND PWR VDDPCI PWR ~PCICLK2 OUT ~PCICLK3 OUT VDDPCI PWR GND PWR PCICLK4 OUT PCICLK5 OUT ~PCICLK_F I/O ~PCICLK6 OUT SCLK IN SDATA I/O GND PWR PIN NAME 24_48MHz/Sel24_48#*~ AVDD48 GND 48MHz/FS3** PD#* GND GND VDDCPU CPUCLK8C1 CPUCLK8T1 VDDCPU GND CPUCLK8C0 CPUCLK8T0 GND VDDA Reset# REF2/FS2* VDDREF GND REF1/FS1* I/O PWR PWR I/O IN PWR PWR PWR OUT OUT PWR PWR OUT OUT PWR PWR OUT I/O PWR PWR I/O DESCRIPTION Frequency select latch input pin / 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V Crystal input,nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Mode selection latch input pin / Hyper Transport output. Mode selection latch input pin / PCI clock output / Hyper Transport output. PCI clock output / Hyper Transport output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output / Hyper Transport output. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. Free running PCI clock not affected by PCI_STOP#. PCI clock output. Clock pin of I2C circuitry 5V tolerant Data pin for I2C circuitry 5V tolerant Ground pin. 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V Ground pin. Frequency select latch input pin / Fixed 48MHz clock output. 3.3V Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 1.8ms. Ground pin. Ground pin. Supply for CPU clocks, 3.3V nominal "Complementary" clocks of differential 3.3V push-pull K8 pair. "True" clocks of differential 3.3V push-pull K8 pair. Supply for CPU clocks, 3.3V nominal Ground pin. "Complementary" clocks of differential 3.3V push-pull K8 pair. "True" clocks of differential 3.3V push-pull K8 pair. Ground pin. 3.3V power for the PLL core. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. 14.318 MHz reference clock / Frequency select latch input pin. Ref, XTAL power supply, nominal 3.3V Ground pin. 14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
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ICS950403
Advance Information
General Description
The ICS950403 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary clock signals for Clawhammer and Sledgehammer with AMD, VIA or ALI systems. The ICS950403 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Power Groups
Pin Number AVDD 2 29 29 43 VDD 9 16, 19 35, 38 46 GND 5 27, 30 33 42 GND 10 15, 20 34, 39 47 PCICLK/HTTCLK Outputs PCICLK Outputs CPU outputs REF Description Crystal 48MHz fixed, Fix Analog, Fix Digital CPU Master Clock, CPU Analog
Mode Functionality Tables
ModeA 0 0 1 1 ModeB 0 1 0 1 Pin7 HTTCLK1 HTTCLK1 PCICLK7 HTTCLK1 Pin8 HTTCLK2 HTTCLK2 PCICLK8 PCICLK8 Pin11 PCICLK9 HTTCLK3 PCICLK9 PCICLK9
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ICS950403
Advance Information
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
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Not acknowledge stoP bit
4
ICS950403
Advance Information
Table1: Frequency Selection Table
Bit5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit4 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit3 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit2 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 150.00 180.00 210.00 240.00 270.00 233.33 266.67 300.00 100.00 133.33 166.66 200.00 103.00 137.33 171.66 206.00 154.50 185.40 216.30 247.20 278.10 240.33 274.67 309.00 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00 66.67 66.67 66.66 66.67 68.67 68.66 68.66 68.67 61.80 61.80 72.10 61.80 69.53 68.67 68.67 77.25 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 30.00 30.00 35.00 30.00 33.75 33.33 33.33 37.50 33.33 33.33 33.33 33.33 34.33 34.33 34.33 34.33 30.90 30.90 36.05 30.90 34.76 34.33 34.33 38.63
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ICS950403
Advance Information
I C Table: Functionality and Frequency Control Register
Byte 0 Bit 7 Bit Bit Bit Bit Bit Bit 6 5 4 3 2 1 Pin # Name GSR_EN FS Source Control Function Gear Shift Reset Enable SPREAD Enable FS4 FS3 FS2 FS1 FS0 Frequency H/W IIC Select Type RW RW RW RW RW RW RW RW 0 Disable Disable 1 Enable Enable PWD 0 0 0 0 0 0 0 0
2
See Table1: Frequency Selection Table
Bit 0
2
Latch Inputs
IIC
I C Table: Output Control Register
Byte 1 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # 12 24 22 21 18 17 14 13
Name PCICLK10 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
7 6 5 4 3 2 1 0
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
I C Table: Output Control Register
Byte 2 Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 37/36 41/40 45 48 1 28 31 Pin # Name CPUT/C_1 CPUT/C_0 REF2 REF1 REF0 24_48MHz 48MHz WDSEN Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Watchdog Soft Alarm Enable Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 0
Bit 0
I C Table: Output Control Register
Byte 3 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 1 1 1 1 1 1 1 1
2
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ICS950403
Advance Information
I C Table: Read back
Byte 4 Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name WDHRB WDSRB 24_48SEL FS3 FS2 FS1 FS0 Reserved
5 4 3 2 1 0
Control Function WD Hard Alarm Status Read back WD Soft Alarm Status Read back 24_48SEL pin Control FS3 on POR state FS2 on POR state FS1 on POR state FS0 on POR state Reserved
Type R R R R R R R R By By By By By
0 S/W S/W S/W S/W S/W By By By By By
1 Latched Latched Latched Latched Latched -
PWD X X 1 1 1 1 1 0
I C Table: Output Control Register
Byte 5 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # 6 11 8 7 23 -
Name HTTCLK0 PCICLK9/HTTCLK3 PCICLK8/HTTCLK2 PCICLK7/HTTCLK1 PCICLK_F Reserved Reserved Reserved
7 6 5 4 3 2 1 0
Control Function Output Control Output Control Output Control Output Control Output Control Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable -
1 Enable Enable Enable Enable Enable -
PWD 1 1 1 1 1 0 0 0
I C Table: Byte Count Register
Byte 6 Bit Bit Bit Bit Bit 7 6 5 4 3 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 1 1 1 1
Bit 2 Bit 1 Bit 0
2
Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes.
I C Table: Vendor and Revision ID Register
Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function REVISION ID Type R R R R R R R R 0 1 PWD 0 0 0 0 0 0 0 1
VENDOR ID
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ICS950403
Advance Information
I C Table: Output Control Register
Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
7 6 5 4 3 2 1 0
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 0 0 0 0 0 0 0 0
I C Table: Watchdog Timer Register
Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit Bit Bit Bit 3 2 1 0 Pin # Name Reserved Reserved Reserved WD4 WD3 WD2 WD1 WD0 Control Function Reserved Reserved Reserved These bits represent X*290ms the watchdog timer will wait before it goes to alarm mode. Default is 16 X 290ms =4.64 seconds Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 1 0 0 0 0
I C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10 Bit 7 Bit 6 Bit 5 Bit Bit Bit Bit Bit
2
2
Pin # -
Name M/NEN WDEN WDFSEN WD SF4 WD SF3 WD SF2 WD SF1 WD SF0
Control Function M/N Programming Enable Watchdog Enable WD Safe Frequency Mode Writing to these bit will configure the safe frequency as Byte0 bit (5:1)
Type RW RW RW RW RW RW RW RW
0 Disable Disable Latched FS/Byte0 -
1 Enable Enable WD B10 b(4:0) -
PWD 0 0 0 0 0 0 0 1
4 3 2 1 0
I C Table: VCO Frequency Control Register
Byte 11 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Bit 8 The decimal representation of M Div (6:0) + 2 is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
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ICS950403
Advance Information
I C Table: VCO Frequency Control Register
Byte 12 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0
Control Function The decimal representation of N Div (8:0) + 8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table.
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD X X X X X X X X
7 6 5 4 3 2 1 0
I C Table: Spread Spectrum Control Register
Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Control Function These Spread Spectrum bits will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming.
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD X X X X X X X X
7 6 5 4 3 2 1 0
I C Table: Spread Spectrum Control Register
Byte 14 Bit Bit Bit Bit Bit 7 6 5 4 3 Pin # Name Reserved Reserved SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Reserved Reserved It is recommended to use ICS Spread % table for spread programming. Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 X X X X X X
Bit 2 Bit 1 Bit 0
2
I C Table: Output Divider Control Register
Byte 15 Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 Pin # Name PCI / HTTDiv3 PCI / HTTDiv2 PCI / HTTDiv1 PCI / HTTDiv0 CPU Div3 CPU Div2 CPU Div1 CPU Div0 Control Function PCICLK/HTTCLK divider ratio can be configured via these 4 bits individually. CPU divider ratio can be configured via these 4 bits individually. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
See Table 2: Divider Ratio Combination Table
Bit 1 Bit 0
See Table 2: Divider Ratio Combination Table
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ICS950403
Advance Information
Table 2: Divider Ratio Combination Table
Divider (3:2) 01 10 1 2 0000 0100 1000 00 2 4 0001 0101 1001 01 3 6 0010 0110 1010 10 5 10 0011 0111 1011 11 7 14 LSB Address Div Address Div Address Bit 00
11 MSB 4 8 1100 8 16 1101 12 24 1110 20 40 1111 28 56 Div Address Div
I C Table: Output Divider Control Register
Byte 16 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Divider (1:0)
Pin # -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
7 6 5 4 3 2 1 0
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD X X X X X X X X
I C Table: Output Divider Control Register
Byte 17 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name Reserved Reserved Reserved CPUINV Reserved Reserved Reserved Reserved
7 6 5 4 3 2 1 0
Control Function Reserved Reserved Reserved CPU Phase Invert Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 Default -
1 Inverse -
PWD X X X X X X X X
I C Table: Group Skew Control Register
Byte 18 Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 Pin # Name Reserved Reserved Reserved Reserved CPUSkw3 CPUSkw2 CPUSkw1 CPUSkw0 Control Function Reserved Reserved Reserved Reserved All other clocks CPUCLKT/C Skew Control Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 0 0
See Table 3: 7-Steps Skew Programming Table
Bit 0
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ICS950403
Advance Information
Table 3: 7-Steps Skew Programming Table
7 Step 11 10 01 00 MSB
2
11 900 ps N/A N/A N/A
10 750 ps N/A N/A N/A
01 600 ps N/A N/A N/A
00 450 ps 300 ps 150 ps 0.0 ps
LSB
I C Table: Group Skew Control Register
Byte 19 Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 Pin # Name PCISkw3 PCISkw2 PCISkw1 PCISkw0 PCI/HTTSkw3 PCI/HTTSkw2 PCI/HTTSkw1 PCI/HTTSkw0 Control Function CPU-PCICLK Skew Control Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 0 0
See Table 3: 7-Steps Skew Programming Table
-
CPU-PCICLK /HTTCLK Skew Control
See Table 3: 7-Steps Skew Programming Table
Bit 0
2
I C Table: Group Skew Control Register
Byte 20 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
7 6 5 4 3 2 1 0
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 1 1 1 1 1 1 1 1
I C Table: Slew Rate Control Register
Byte 21 Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved ASEL AEN Control Function Reserved Reserved Reserved Reserved Reserved Reserved Async Frequency Select AGP/PCI/ Freq Source Select Type RW RW RW RW RW RW RW RW 0 66.0MHz Fix PLL 1 75.4MHz CPU PLL PWD 0 0 0 0 0 0 0 1
Bit 1 Bit 0
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ICS950403
Advance Information
I C Table: Drive Strength Control Register
Byte 22 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
2
Pin # -
Name PCI9/HTT3 DrCntrl PCI6Drv PCI3Drv PCI2Drv PCIFDrv 24_48Drv PCI8/HTT2 DrCntrl PCI7/HTT1 DrCntrl
Control Function PCICLK9/HTTCLK3 Drive Strength Control PCICLK6 Drive Strength Control PCICLK3 Drive Strength Control PCICLK2 Drive Strength Control PCICLK_F Drive Strength Control 24_48MHz Drive Strength Control PCICLK8/HTTCLK2 Drive Strength Control PCICLK7/HTTCLK1 Drive Strength Control
Type RW RW RW RW RW RW RW RW
0 1X 1X 1X 1X 1X 1X 1X 1X
1 2X 2X 2X 2X 2X 2X 2X 2X
PWD 1 1 1 1 1 1 1 1
I C Table: Slew Rate Control Register
Byte 23 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name Reserved Reserved Reserved Reserved PCISlw1 PCISlw0 PCISlw1 PCISlw0
7 6 5 4 3 2 1 0
Control Function Reserved Reserved Reserved Reserved PCICLK(1:0) Slew Rate Control PCICLK(10, 5:4) Slew Rate Control
Type RW RW RW RW RW RW RW RW
0 -
1 -
PWD 1 0 1 0 1 0 1 0
I C Table: Slew Rate Control Register
Byte 24 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name REFSlw1 REFSlw0 48MSlw1 48MSlw0 Reserved Reserved Reserved Reserved Control Function REF(2:0) Slew Rate Control 48MHz Slew Rate Control Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 1 0 1 0 1 0 1 1
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Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +3.8 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Input frequency Input Capacitance1 Clk Stabilization1
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66
CONDITIONS
MIN 2 V SS - 0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz
MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 180 600 mA mA MHz pF pF ms
IDD3.3OP100 CL = 0 pF; Select @ 100MHz IDD3.3OP133 CL = 0 pF; Select @ 133MHz PD Fi CIN CINX TSTAB VDD = 3.3 V; Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq. 10 27 14.318
16 5 45 3
Guaranteed by design, not 100% tested in production.
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Advance Information
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output Low Current Rise Edge Rate Fall Edge Rate VDIFF
1 1
SYMBOL ZO VOH2B VOL2B IOL2B
CONDITIONS VO = VX
MIN 15 1 18 2 2
TYP
MAX 55 1.2 0.4 7 7
VOL = 0.3 V Measured from 20-80% Measured from 80-20% Differential Voltage, Measured @ the Hammer test load (single-ended measurement) Change in V DIFF_DC magnitude, Measured @ the Hammer test load (single-ended measurement) Common Mode Voltage, Measured @ the Hammer test load (single-ended measurement) Change in Common Mode Voltage, Measured @ the Hammer test load (singleended measurement)
UNITS V V mA V/ns V/ns
0.4
2.3
V
DVDIFF
-150
150
mV
VCM
1.05
1.45
V
DVCM
-200
200
mV
dt2B VT = 50% 45 53 % Duty Cycle1 1 tjcyc-cyc2B V T = VX 0 200 ps Jitter, Cycle-to-cycle Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (V TR-V CP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
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ICS950403
Advance Information
Electrical Characteristics - PCICLK/HTTCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate Fall Edge Rate1 Duty Cycle1 Jitter, Cycle-tocycle1
1
SYMBOL VOH1 VOL1 I OH1 I OL1
CONDITIONS IOH = -12 mA IOL = 9.0 mA VOH = 2.0 V VOL = 0.8 V Measured from 20-60% Measured from 60-20% VT = 50% Measured on rising edge @ 1.5V
MIN 2.4
TYP
10 1 1 45
MAX UNITS V 0.4 V -15 mA mA 4 4 55 250 V/ns V/ns % ps ps W
dt1 tjcyc-cyc2B
Jitter, Accumulated1 Output Impedance
1
-1000 ZO VO = VX 12
1000 55
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate Fall Edge Rate1 Duty Cycle1 Jitter, Cycle-tocycle1
1
SYMBOL VOH1 VOL1 IOH1 IOL1
CONDITIONS IOH = -12 mA IOL = 9.0 mA VOH = 2.0 V VOL = 0.8 V Measured from 20-60% Measured from 60-20% VT = 50% Measured on rising edge @ 1.5V
MIN 2.4
TYP
10 1 1 45
MAX UNITS V 0.4 V -15 mA mA 4 4 55 250 V/ns V/ns % ps ps W
dt1 tjcyc-cyc2B
Jitter, Accumulated1 Output Impedance
1
-1000 ZO VO = VX 12
1000 55
Guaranteed by design, not 100% tested in production.
0732--01/27/03
15
ICS950403
Advance Information
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate1 Fall Edge Rate1 Duty Cycle1 Jitter, Cycle-tocycle1 Jitter, Accumulated1
1
SYMBOL VOH5 VOL5 IOH5 IOL5
CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V Measured from 20-80% Measured from 80-20% VT = 50% Mesured on rising edge @ 1.5V
MIN 2.4
TYP
16 0.5 0.5 45 0 -1000
MAX UNITS V 0.4 V -22 mA mA 2 2 55 1000 1000 V/ns V/ns % ps ps
dt5 tjcyc-cyc2B
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate1 Fall Edge Rate1 Duty Cycle1 Jitter, Absolute1 Jitter, Cycle-tocycle1 Jitter, Cycle-tocycle1 Output Impedance SYMBOL VOH5 VOL5 I OH5 I OL5 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V Measured from 20-80% Measured from 80-20% VT = 50% VT = 1.5 V VT = VX, for 24_48MHz clock VT = VX, for 48MHz clock VO = VX MIN 2.4 TYP MAX UNITS V 0.4 V -22 mA mA 2 2 55 1 500 200 60 V/ns V/ns % ns ps ps W
16 0.5 0.5 45 -1 0 0 20
dt5 tjabs5 tjcyc-cyc2B tjcyc-cyc2B ZO
0732--01/27/03
16
ICS950403
Advance Information
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS950403 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of PowerOn reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS950403
Advance Information
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950403yFT
Example:
ICS XXXXXX y F - T
Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0732--01/27/03
18

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